Resume¶
Download¶
Laxmidhar Barik¶
VLSI Design Engineer
NIT Raipur, Chhattisgarh — 492010
lbarik.mtech2023@nitrr.ac.in
+91-9937876586
linkedin.com/in/Laxmidhar Barik
github.com/Blaxmidhar
Education¶
| Degree | Institution | Year | CGPA/% |
|---|---|---|---|
| M.Tech, VLSI Design & Embedded Systems | NIT Raipur, Chhattisgarh | 2023–2025 | 9.12 |
| B.Tech, Electrical & Electronics | BPUT, Odisha | 2018–2022 | 9.04 |
| Intermediate (12th) | CHSE, Odisha | 2015–2017 | 83.89% |
| 10th | BSEO, Odisha | 2015 | 88.83% |
Achievements¶
- GATE 2023 (EE): AIR 3193
- GATE 2024 (EE): AIR 6005
Experience¶
Teaching Assistant — HDV (Hardware Design using Verilog)
NIT Raipur · Aug 2024 – Dec 2024
Assisted Dr. Ashish Kumar. Conducted lab sessions on Verilog coding (Half Adder, Full Adder, Encoders, Decoders, Flip-Flops, FSM). Supported students using Xilinx ISE and Vivado.
Teaching Assistant — Computer Programming in C++
NIT Raipur · Jan 2025 – May 2025
Assisted Dr. Prateek Dholakia in teaching B.Tech (1st semester) students C++ fundamentals including OOP, pointers, arrays, and functions.
Technical Skills¶
| Category | Skills |
|---|---|
| Languages | C, C++, Verilog, VHDL, SystemVerilog, Unix, TCL |
| Design Tools | Cadence Virtuoso, Xilinx ISE/Vivado, LTspice, HSPICE, MATLAB, Silvaco TCAD, OriginPro |
| Open Source | EDA Playground, Yosys, Magic, Ngspice, OpenSTA, OpenLane, Qflow |
| Verification | SystemVerilog testbenches, UVM architecture |
Publications¶
- Laxmidhar Barik, S. Samal, A. Kumar — Sensing and Imaging (Communicated)
- S. Samal, Laxmidhar Barik et al. — IEEE DevIC 2025, pp. 380–384. DOI: 10.1109/DevIC63749.2025
- Yogendra Kumar, Laxmidhar Barik et al. — EDAS Malaysia ICECE 2025 (Accepted)
- Laxmidhar Barik et al. — IEEE BIO-SENSORS 2025, USA (Submitted)
Certifications¶
- INUP-i2i 18th User Awareness Workshop, IIT Delhi (Dec 2024)
- Digital Electronics — NPTEL
- SystemVerilog for Verification — Udemy